The first semiconductor chips held two transistors each. Subsequent advances added more and more transistors, and, as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as small-scale integration (SSI), improvements in technique led to devices with hundreds of logic gates, known as medium-scale integration (MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and billions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use. Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are VLSI or better.
As of early 2008, billion-transistor processors are commercially available, an example of which is Intel's Montecito Itanium chip. This is expected to become more commonplace as semiconductor fabrication moves from the current generation of 65 nm processes to the next 45 nm generations (while experiencing new challenges such as increased variation across process corners). Another notable example is Nvidia's 280 series GPU. This GPU is unique in the fact that almost all of its 1.4 billion transistors are used for logic, in contrast to the Itanium, whose large transistor count is largely due to its 24 MB L3 cache. Current designs, as opposed to the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the highest efficiency (sometimes by bending or breaking established design rules to obtain the last bit of performance by trading stability).
Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway for saving microchip area by minimizing the interconnect fabrics area. This is obtained by repetitive arrangement of rectangular macro blocks which can be interconnected using wiring by abutment. An example is partitioning the layout of an adder into a row of equal bit slices cells. In complex designs this structuring may be achieved by hierarchical nesting.
Structured VLSI design had been popular in the early 1980s, but lost its popularity later because of the advent of placement and routing tools wasting a lot of area by routing, which is tolerated because of the progress of Moore's Law. When introducing the hardware description language KARL in the mid' 1970s, Reiner Hartenstein coined the term "structured VLSI design" (originally as "structured LSI design"), echoing Edsger Dijkstra's structured programming approach by procedure nesting to avoid chaotic spaghetti-structured programs.
As microprocessors become more complex due to technology scaling, microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon:
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ModelSim PE Student Edition is a free download of the industry leading ModelSim HDL simulator for use by students in their academic coursework.
ModelSim PE Student Edition Highlights
- Support for both VHDL and Verilog designs (non-mixed).
- Intelligent, easy-to-use graphical user interface with TCL interface.
- Project manager and source code templates and wizards.
LASI (LAyout System for Individuals) is a "general purpose" layout and design system originally intended for integrated circuits. It is versatile enough that it can be used for ICs, MEMS, discrete devices, schematics, PC boards and project documentation drawings. LASI is a "precision" drawing system where figures are always precisely located. LASI is intended for both educational and professional use.
For students LASI teaches a better understanding of what you are really doing. To use LASI, you need to know something about your technology, the physics involved and have some circuit intuition, not just know how to run software. It is for people who still consider IC design something of an art.
A very simple version of LASI was written for MS-DOS in the mid-80's by the author to be used for his own IC design. When Windows 95 came out, LASI was rewritten as version 6 for Windows. The current version 7 is more elegant, functional and runs on all Windows versions.
The original intention of LASI was to aid commercial design systems. It still has that purpose since layout work can be done on any Windows PC or Laptop, on Linux systems using Wine, and then be transferred using common formats such as GDS.
LASI also runs portably. You can install the system on a flash drive or other removable drive and work directly on any layouts you might have on the drive. Portable operation lets you run on a PC without leaving data on that PC. This is handy for presentations.
Drawings are built from hierarchical cells stored as individual TLC (Transportable Layout Cells) files. TLC files can be easily traded between different drawings. TLC files are in XML or optionally the original text format.
LASI consists of a main drawing editor program and several "utility" programs. These utilities include GDS, CIF and DXF format converters, a user programmable bitmap based DRC, a basic matrix router, and a Spice netlist compiler that extracts Spice circuit files from both schematic and layout and can do an LVS compare. The utilities can run independently or directly out of the editor.
LASI compiles Spice net files but does not do simulations. There are good Spice simulators available already. Most simulators can run directly out of the main editor or the Spice compile utility.
Although fairly well developed by now, LASI is still an ongoing project. There is always something that you can add, improve or fix. Watch this site for the latest version, approximately every month or two.
|Adc - Dac|
This chart is not complete:
One of the basic building blocks in MEMS processing is the ability to deposit thin films of material with a thickness anywhere between a few nanometres to about 100 micrometres.
There is a type of physical deposition.
There are 2 types of chemical deposition.Thermal Oxidation
Patterning in MEMS is the transfer of a pattern into a material.
Lithography in MEMS context is typically the transfer of a pattern into a photosensitive material by selective exposure to a radiation source such as light. A photosensitive material is a material that experiences a change in its physical properties when exposed to a radiation source. If a photosensitive material is selectively exposed to radiation (e.g. by masking some of the radiation) the pattern of the radiation on the material is transferred to the material exposed, as the properties of the exposed and unexposed regions differs.
This exposed region can then be removed or treated providing a mask for the underlying substrate. Photolithography is typically used with metal or other thin film deposition, wet and dry etching.
Bulk micromachining is the oldest paradigm of silicon based MEMS. The whole thickness of a silicon wafer is used for building the micro-mechanical structures. Silicon is machined using various etching processes. Anodic bonding of glass plates or additional silicon wafers is used for adding features in the third dimension and for hermetic encapsulation. Bulk micromachining has been essential in enabling high performance pressure sensors and accelerometers that have changed the shape of the sensor industry in the 80's and 90's.
Surface micromachining uses layers deposited on the surface of a substrate as the structural materials, rather than using the substrate itself. Surface micromachining was created in the late 1980s to render micromachining of silicon more compatible with planar integrated circuit technology, with the goal of combining MEMS and integrated circuits on the same silicon wafer. The original surface micromachining concept was based on thin polycrystalline silicon layers patterned as movable mechanical structures and released by sacrificial etching of the underlying oxide layer. Interdigital comb electrodes were used to produce in-plane forces and to detect in-plane movement capacitively. This MEMS paradigm has enabled the manufacturing of low cost accelerometers for e.g. automotive air-bag systems and other applications where low performance and/or high g-ranges are sufficient. Analog Devices have pioneered the industrialization of surface micromachining and have realized the co-integration of MEMS and integrated circuits.
Both bulk and surface silicon micromachining are used in the industrial production of sensors, ink-jet nozzles, and other devices. But in many cases the distinction between these two has diminished. A new etching technology, deep reactive-ion etching, has made it possible to combine good performance typical of bulk micromachining with comb structures and in-plane operation typical of surface micromachining. While it is common in surface micromachining to have structural layer thickness in the range of 2 µm, in HAR silicon micromachining the thickness can be from 10 to 100 µm. The materials commonly used in HAR silicon micromachining are thick polycrystalline silicon, known as epi-poly, and bonded silicon-on-insulator (SOI) wafers although processes for bulk silicon wafer also have been created (SCREAM). Bonding a second wafer by glass frit bonding, anodic bonding or alloy bonding is used to protect the MEMS structures. Integrated circuits are typically not combined with HAR silicon micromachining. The consensus of the industry at the moment seems to be that the flexibility and reduced process complexity obtained by having the two functions separated far outweighs the small penalty in packaging. A comparison of different high-aspect-ratio microstructure technologies can be found in the HARMST article.
A forgotten history regarding surface micromachining revolved around the choice of polysilicon A or B. Fine grained (<300A grain size, US4897360), post strain annealed pure polysilicon was advocated by Prof Henry Guckel (U. Wisconsin); while a larger grain, doped stress controlled polysilicon was advocated by the UC Berkeley group.
In one viewpoint MEMS application is categorized by type of use.
In another view point mems applications are categorized by the field of application(Commercial applications include):